A programmable device (PD) is a well-known type of integrated circuit (IC) that may be programmed by a user to perform specified logic functions. There are different types of programmable devices, such as programmable logic arrays (PLAs) and complex programmable logic devices (CPLDs). One type of programmable device, called a field programmable gate array (FPGA), is very popular because of a superior combination of capacity, flexibility, time-to-market, and cost. An FPGA typically includes an array of configurable logic blocks (CLBs) and programmable input/output blocks (IOBs). The CLBs and IOBs are interconnected by a programmable interconnect structure. The CLBs, IOBs, and interconnect structure are typically programmed by loading a stream of configuration data (bitstream) from an external source into internal configuration memory cells that define how the CLBs, IOBs, and interconnect structure are configured. Thus, the collective states of the individual configuration memory cells determine the function of the FPGA.
A well-studied occurrence in circuitry is called Single Event Upset (SEU). SEU is an inadvertent change in state of a circuit caused by external energy source such as, for example, cosmic rays, alpha particles, energetic neutrons, and the like. The energetic particles may randomly strike a semiconductor device and penetrate into the active regions (e.g., transistor source and drain regions) of the semiconductor device. These particle strikes create pairs of electrons and holes, which in turn cause undesirable transients that may upset circuit elements such as, for example, flipping the logic state of a latch or other memory element. Such an upset will result in data corruption and can lead to system corruption or failure. As fabrication geometries and supply voltages continue to decrease and circuit densities and transistor counts continue to increase, SEU problems become more severe.
The sensitivity of a static ram (SRAM) cell to incident neutron or alpha or other charged particles depends upon a number of factors, including the critical charge (Qcrit) and the SRAM cell target area. Qcrit is a measure of the charge required to flip the state of an SRAM cell or latch and depends upon many factors, including the capacitance on the cross-coupled nodes of the SRAM cell or latch. Efforts to maximize Qcrit and minimize target area can lead to lowered SEU susceptibility. However, these two factors are often working in opposition. While the scaling of technology will reduce the target area, it will also lead to significantly reduced capacitance, and hence reduced Qcrit. Hence, SEU rates may increase from one technology generation to the next (e.g., 45 nm to 32 nm).
It may be necessary to develop special non-standard processes to maximize the Qcrit for small area cells, in order to keep the SEU rate at an acceptable level. Such non-standard processes have been demonstrated to increase Qcrit and hence improve the SEU. However, a solution that uses commonly available processes utilized in standard CMOS technology (e.g., with few or no additional masks or process steps) would have a clear cost and time-to-market advantage.
There is a need to address the above identified issues. The present invention addresses such a need.